1. Technical Field
The present disclosure relates to clock and data recovery circuits, and more particularly to clock and data recovery circuits operating at high speeds and having reduced phase errors.
2. Discussion of the Related Art
In high-speed data communications, serial data transfers have more advantages compared with parallel data transfers; for example, serial data transfers require fewer channels and induce less interference between signals. In the case of transferring serial data signal at high speeds, a frequency clock for recovering serial data is generally recovered from the serial data signal. In order to accurately recover the serial data included in the serial data signal, the phase of the received serial data signal and the phase of the recovered frequency clock need to be synchronized. A circuit that recovers the frequency clock to be synchronized with the data signal is referred to as a clock and data recovery (CDR) circuit.
In U.S. Pat. No. 6,002,279 and U.S. Pat. No. 6,122,336, CDR methods using phase interpolators are disclosed. The methods according to U.S. Pat. No. 6,002,279 and U.S. Pat. No. 6,122,336, however, are difficult to adapt to spread spectrum clocking (SSC).
Because a clock signal typically has a single frequency, energy distribution of the clock signal is concentrated in a narrow frequency band, and the energy distribution has a large peak value. In the case of the clock signal having a high frequency (e.g., several GHz), a length of a circuit wire becomes similar to a wavelength of the clock signal, and some wires may even operate as an antennas the wavelength is shortened. Thus, electromagnetic radiation of a corresponding frequency and its harmonics may easily occur. In addition, an error between adjacent circuits may be increased because of electromagnetic interference (EMI). Therefore, there exist limits as to how much a clock frequency can be increased.
Accordingly, the SSC technique was introduced for reducing an EMI effect. The SSC technique includes lowering a peak value by spreading the energy distribution concentrated in a narrow frequency band over a large frequency band, thereby reducing the EMI effect at substantially the same energy levels. More specifically, the SSC technique modulates the clock frequency according to a modulation profile having a predetermined rate of change, thereby preventing the EMI effect and increasing a maximum clock frequency, that is, a nominal frequency.
In transferring high-speed serial data with the SSC technique, the serial data signal has a relatively high frequency that constantly changes within a predetermined frequency band. Thus, a CDR circuit capable of constantly keeping up with clock changes and operating at high speeds is required. In a data transfer standard of the Serial Advanced Technology Attachment (SATA), a capability of keeping up with a frequency variation of more than about 0.5%, that is, 5,000 ppm, is required. To satisfy the above condition, a phase detector and a loop filter need to have very high speeds. It is difficult, however, to increase the operating speed and the frequency variation to more than 300 MHz and 2,000 ppm, respectively, in the phase detector and loop filter of a generic digital logic circuit. The limit to the frequency variation may be overcome by adapting a source-coupled logic (SCL) capable of implementing a high-speed logic circuit and by increasing pipeline steps; however, the chip size or power consumption may be considerably increased.
FIG. 1 is a block diagram illustrating a conventional CDR circuit. The conventional CDR circuit of FIG. 1 converts high-speed serial data into low-speed parallel data, and then detects a phase difference of the converted parallel data.
Referring to FIG. 1, the CDR circuit includes a sampler 11, a deserializer (serial-parallel converter) 12, a phase detection logic 13, a loop filter 14, a phase interpolation controller 15, a phase interpolator 16, a frequency divider 17, and a phase-locked loop 18.
The phase-locked loop 18 generates four reference clock signals that respectively have a frequency of f/2 Hz and a phase difference of about 90° between each other. The phase interpolator 16 receives the reference clock signals and adjusts the phases, to generate four recovery clock signals that respectively have a frequency of f/2 Hz and a phase difference of about 90° between each other. The phase interpolator 16 provides the recovery clock signals to the sampler 11.
The frequency divider 17 lowers an inputted frequency by 1/n, and outputs the lowered frequency. That is, the frequency divider 17 transforms the inputted f/2 Hz clock signal into an f/2n Hz clock signal, and then provides the f/2n Hz clock signal as an operating clock of the deserializer 12, the phase detection logic 13, the loop filter 14 and the phase interpolation controller 15.
The sampler 11 samples serial data INPUT having f bps, and provides a sampled signal to the deserializer 12. The deserializer 12 transforms the sampled signal into two n-bit parallel data IDATA and QDATA. At least one of the transformed n-bit parallel data IDATA and QDATA may be provided to the exterior as recovery data DATA.
The phase detection logic 13 generates one of a pulse signal UP and a pulse signal DOWN corresponding to the respective n-bit parallel data IDATA and QDATA. The pulse signals UP/DOWN are used for changing a phase of the operating clock.
The pulse signals UP/DOWN are inputted to the loop filter 14. The loop filter 14 is a kind of digital filter that transforms a high-frequency pulse into low-frequency edges. An output of the loop filter 14 is provided to the phase interpolation controller 15, and then transformed into a phase control signal CTL. The control signal CTL is provided to the phase interpolator 16. The phase interpolator 16 changes phases of the four reference clock signals in response to the phase control signal CTL. The phase interpolator 16 generates the four recovery clock signals, the phases of which are compensated, and provides the four recovery clock signals to the sampler 11.
In the circuit of FIG. 1, because the phase is detected based on the parallel data, the speed burden on the phase detector and the loop filter may be reduced. For example, in case that n is 20, phases of respective 20-bit parallel data are detected, and thus phase control signals are respectively generated. In the case that the SSC technique is applied, however, the phase interpolator adjusts a phase at a relatively slow speed compared to the high speed of the input data. Therefore, the phase interpolator cannot keep up with a frequency variation of the input data, or a phase margin is greatly reduced.